Bluetooth – FPGA – Battery Management – One Tiny Footprint
- General Description
- Block Diagram
- Wireless Radio
- Flash Storage
- Power Management
- Footprint & Layout
- Firmware Information
- Ordering Information
- Schematics & PCB Design
The S1 module combines an FPGA with wireless and battery management suitable for low power applicaions such as wearables or small IoT devices*.
Occupying a volume of just 6 x 12 x 1.6mm, the device can be integrated into very small designs, with little to no external components. Ground and Vcc are the only required connections required for the device to function.
There are 8 exposed IO pins which go directly to the Lattice ICE40UP5K FPGA. These pins may be used as general purpose IO, or serial lines. The FPGA contains two hardware SPI/I2C blocks routable to any pins, as well as I3C compatible IO for use with a user provided I3C IP block. The FPGA features 5280 LUTs, 1Mb of SPRAM and 8 DSP blocks.
The wireless portion of the module uses a Nordic nRF52811 Bluetooth SoC featuring support for Bluetooth 5.2 (with direction finding) as well as Zigbee, Thread or Bluetooth Mesh. The SoC is user programmable via the exposed debug port, or may be preloaded with our SuperStack Firmware should you choose. Additionally, 2 ADC lines are also conveniently exposed for general purpose use.
To manage power, the module contains a dedicated PMIC (Power management IC). It integrates a Li charger, battery monitor (via an nRF52811 ADC pin), three buck-boost regulator outputs and one LDO regulator output. All of which are independently configurable. This architecture allows the module to output several voltage rails for external circuits, one of which can be boosted to 5.5V, even from a single Lithium cell. Additionally, the voltage rails may be dynamically adjusted or switched off all-together to save power.
Finally, 4Mb of on board flash storage is available for holding the FPGA boot data, and any remaining space may be used for user application data.
The device hardare design is open source and is licensed under a Creative Commons Attribution 4.0 International License.
- Bluetooth 5.2 Supporting Direction Finding
- 5k FPGA with 8 DSP Blocks & Two Serial Drivers
- 4 Mb Flash Storage
- 8 GPIO Pins
- 2 ADC Pins
- 4 Configurable Voltage Outputs
- Li Battery Charger
- No External Passive Components Needed
- High Speed & Time Critical Sensor DSP
- Lower Power Data Pre-Processing
- Parallel Data Processing
- Realtime AI Inferencing
- Remote Machine Learning
- Bespoke AI Algorithm Deployment
- Bespoke DSP Algorithm Deployment
- Wearable Devices
- Small Form Factor IoT Devices
- Implantable or Medical Devices**
- Remote Interfacing & Sensing
- Sensor Data Collection & ML Data Labeling
**Our devices and components used within are not pre-qualified for any kind of regulatory requirements, medical or life support applications. You will need to fully qualify the device in order to use it in such applications and take complete responsibility fully indemnifying Silicon Witchery AB for any failure arising from use of our devices or software.
|1, 20, 14||GND||–||Ground. Pins 1 and 20 are close to the antenna and must connect to a good ground plane for optimal antenna performance. Pin 14 isn’t as critical, however is strongly recommended when high currents may be required from the power rails, or when using the battery charging feature.|
|2||USBN||IO||USB data – signal. May be used as general purpose complementary IO.|
|5||USBP||IO||USB data + signal. May be used as general purpose complementary IO.|
|2, 3, 4, 5, 6, 7, 8, 9||D1 - D8||IO||General purpose IO pins directly connected to the FPGA. Signal voltage range is set internally to the VIO pin.|
|10||VCHG||I||Main power input|
|15, 16||ADC1, ADC2||I(O*)|
The S1 Module comes pre-programmed with the SuperStack Runtime so do not need factory programming if a custom Bluetooth application is not required.
However it is possible to program or re-program the S1 module via the exposed programming pins.
|VCHG-MAX||Charge input terminal voltage||V|
|VBAT-MAX||Battery terminal voltage||V|
|PVO1||VOUT1 power draw||W|
|PVO2||VOUT2 power draw||W|
|Tamb||Operating ambient temperature||°C|
|VESD-HBM||ESD - Human body model||V|
|VESD-CDM||ESD - Charged device model||V|
VCHG = 0V, VBAT = 3.7V unless specified
|TRF||1Mbps cont. TX radio temperature *||°C|
|TRF+FPGA||Full speed FPGA temperature *||°C|
|TCHG||Charge IC temperature VCHG = 5V *||°C|
* lab measured values
|VCHG||Charger supply voltage||V|
|VBAT||Battery input voltage||V|
|VBAT-CV||Charge constant voltage range||V|
|IBAT-CC||Charge constant current range||mA|
|VVO1||Configurable rail 1 V range||V|
|VVO1||Configurable rail 1 current||mA|
|VVO2||Configurable rail 2 V range||V|
|IVO2||Configurable rail 2 current||mA|
|VADC||Usable ADC range||V|
|IIO||GPIO/Bus current source/sink||mA|
|Isleep||Sleep mode current||mA|
|IRF-TX||RF TX mode current||mA|
|IRF-RX||RF RX mode current||mA|
|IFPGA||FPGA active current||mA|
|VESD-HBM||Max transmit power||+4||dBm|
|VESD-CDM||Whip antenna gain||3||dBi|