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S1 Module

Launching Q4 - Preliminary datasheet

Bluetooth – FPGA – Battery Management – One Tiny Footprint

Silicon Witchery S1 Module


  1. General Description
    1. Features
    2. Use Cases
    3. Applications
  2. Block Diagram
  3. Pinout
  4. Wireless Radio
    1. Programming Interface
    2. ADC
    3. FPGA & Flash Storage Interface
    4. Power Options
    5. Recommended Tools & Software
  5. FPGA
    1. Programming Interface
    2. Auto-Boot
    3. IO
    4. Power Options
    5. Recommended Tools & Software
  6. Flash Storage
  7. Power Management
    1. How to not Blow Up the Module
    2. Battery Charging
    3. Buck-Boost Supplies
    4. Low Dropout Regulator
  8. Ratings
    1. Absolute Maximum Ratings
    2. Electrostatic Discharge (ESD)
    3. Thermal Information
    4. DC Characteristics & Power Consumption
    5. RF Characteristics
  9. Footprint & Layout
    1. PCB Footprint Guide
    2. Antenna Considerations
    3. Mechanical Drawing
  10. Firmware Information
  11. Ordering Information
  12. Schematics & PCB Design

General Description

The S1 module combines an FPGA with wireless and battery management suitable for low power applications such as wearables or small IoT devices*.

Occupying a volume of just 6 x 12 x 1.6mm, the device can be integrated into very small designs, with little to no external components. Ground and Vcc are the only required connections required for the device to function.

There are 8 exposed IO pins which go directly to the Lattice ICE40UP5K FPGA. These pins may be used as general purpose IO, or serial lines. The FPGA contains two hardware SPI/I2C blocks rotatable to any pins, as well as I3C compatible IO for use with a user provided I3C IP block. The FPGA features 5280 LUTs, 1Mb of SPRAM and 8 DSP blocks.

The wireless portion of the module uses a Nordic nRF52811 Bluetooth SoC featuring support for Bluetooth 5.2 (with direction finding) as well as Zigbee, Thread or Bluetooth Mesh. The SoC is user programmable via the exposed debug port, or may be preloaded with our SuperStack Firmware should you choose. Additionally, 2 ADC lines are also conveniently exposed for general purpose use.

To manage power, the module contains a dedicated PMIC (Power management IC). It integrates a Li charger, battery monitor (via an nRF52811 ADC pin), three buck-boost regulator outputs and one LDO regulator output. All of which are independently configurable. This architecture allows the module to output several voltage rails for external circuits, one of which can be boosted to 5.5V, even from a single Lithium cell. Additionally, the voltage rails may be dynamically adjusted or switched off all-together to save power.

Finally, 4Mb of on board flash storage is available for holding the FPGA boot data, and any remaining space may be used for user application data.

The device hardare design is open source and is licensed under a Creative Commons Attribution 4.0 International License.


  • Bluetooth 5.2 Supporting Direction Finding
  • 5k FPGA with 8 DSP Blocks & Two Serial Drivers
  • 4 Mb Flash Storage
  • 8 GPIO Pins
  • 2 ADC Pins
  • 4 Configurable Voltage Outputs
  • Li Battery Charger
  • No External Passive Components Needed

Use Cases

  • High Speed & Time Critical Sensor DSP
  • Lower Power Data Pre-Processing
  • Parallel Data Processing
  • Realtime AI Inferencing
  • Remote Machine Learning
  • Bespoke AI Algorithm Deployment
  • Bespoke DSP Algorithm Deployment


  • Wearable Devices
  • Small Form Factor IoT Devices
  • Implantable or Medical Devices**
  • Remote Interfacing & Sensing
  • Sensor Data Collection & ML Data Labeling

**Our devices and components used within are not pre-qualified for any kind of regulatory requirements, medical or life support applications. You will need to fully qualify the device in order to use it in such applications and take complete responsibility fully indemnifying Silicon Witchery AB for any failure arising from use of our devices or software.

Block Diagram

S1 Module Block Diagram


S1 Module Pinout

Pin NumberSignalDirectionDescription
1, 20, 14GNDGround. Pins 1 and 20 are close to the antenna and must connect to a good ground plane for optimal antenna performance. Pin 14 isn’t as critical, however is strongly recommended when high currents may be required from the power rails, or when using the battery charging feature.
2USBNIOUSB data – signal. May be used as general purpose complementary IO.
5USBPIOUSB data + signal. May be used as general purpose complementary IO.
2, 3, 4, 5, 6, 7, 8, 9D1 - D8IOGeneral purpose IO pins directly connected to the FPGA. Signal voltage range is set internally to the VIO pin.
10VCHGIMain power input
15, 16ADC1, ADC2I(O*) 

Wireless Radio

Programming Interface

The S1 Module comes pre-programmed with the SuperStack Runtime so do not need factory programming if a custom Bluetooth application is not required.

However it is possible to program or re-program the S1 module via the exposed programming pins.

S1 Module JLINK Connection Diagram


FPGA & Flash Storage Interface

Power Options


Programming Interface



Power Options

Flash Storage

Power Management

How to not Blow Up the Module

Battery Charging

Buck-Boost Supplies

Low Dropout Regulator


Absolute Maximum Ratings

VCHG-MAXCharge input terminal voltage  V
VBAT-MAXBattery terminal voltage  V
VIO-MAXBus/GPIO voltage  V
VADC-MAXADC voltage  V
PVO1VOUT1 power draw  W
PVO2VOUT2 power draw  W
TambOperating ambient temperature  °C
TstgStorage temperature  °C

Electrostatic Discharge (ESD)

VESD-HBMESD - Human body model V
VESD-CDMESD - Charged device model V

Thermal Information

VCHG = 0V, VBAT = 3.7V unless specified

TRF1Mbps cont. TX radio temperature * °C
TRF+FPGAFull speed FPGA temperature * °C
TCHGCharge IC temperature VCHG = 5V * °C

* lab measured values

DC Characteristics & Power Consumption

VCHGCharger supply voltage  V
VBATBattery input voltage  V
VBAT-CVCharge constant voltage range  V
IBAT-CCCharge constant current range  mA
VVO1Configurable rail 1 V range  V
VVO1Configurable rail 1 current  mA
VVO2Configurable rail 2 V range  V
IVO2Configurable rail 2 current  mA
VADCUsable ADC range  V
IIOGPIO/Bus current source/sink  mA
IsleepSleep mode current  mA
IRF-TXRF TX mode current  mA
IRF-RXRF RX mode current  mA
IFPGAFPGA active current  mA

RF Characteristics

VESD-HBMMax transmit power+4dBm
VESD-CDMReceive sensitivity-96dBm
VESD-CDMWhip antenna gain3dBi

Footprint & Layout

PCB Footprint Guide

Antenna Considerations

Mechanical Drawing

Firmware Information

Ordering Information

Schematics & PCB Design